talent skill-synthesis - Lucres

Talent Search

Rajesh Uppara · @rajeshu

Seniour design engineer - II, Alphawave Semi

3+ Years

GOWRI SHANKAR KOTA · @gowri

Fresher

VHDL Verilog FPGA RTL Design Synthesis Simulation Testbench Timing Analysis Logic Synthesis.circuit design soldering digital circuits

Sandeep M G · @sandeepmg

Fresher

Timing closure Floorplanning Clock tree synthesis Place and Route Static timing analysis Physical verification Signal integrity analysis