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system verilog
SHWETA JADHAV
Hardware Design Engineer
2+ years
RTL Design
AXI4
AXILITE
Digital Circuits
AXIStream
Verilog
TCL Scripting
Basics of System verilog
Prashanth S
Bachelor of Technology (BTech)
digital electronics
verilog
system verilog
system verilog assertion
universal verification methodology
Pavan Kumar
B.TECH
Bengaluru, India
verilog
uvm
system verilog
digital electronics
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