Lucres
Post Job
Sign in
Lucres
Home
About Us
Contact Us
Jobs
Talent
Talent Search
Clear all
×
Filter
Clear all
Locations
Skills
testbench architecture
GOWRI SHANKAR KOTA
·
@gowri
Fresher
VHDL
Verilog
FPGA
RTL Design
Synthesis
Simulation
Testbench
Timing Analysis
Logic Synthesis.
circuit design
soldering
digital circuits
Anand Manaji
·
@anandmanaji
Fresher
ASIC design
debugging techniques
scripting languages
hardware verification
code optimization
systemVerilog
UVM methodology
constrained random testing
coverage-driven verification
virtual sequences
assertion-based verification
testbench architecture
scoreboard implementation
functional coverage.
«
1
(current)
»
Home
About Us
Contact Us
Jobs
Talent
