talent skill-verilog - Lucres

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Pavan Kumar · @pavankumar

Fresher

Bengaluru, India

verilog uvm system verilog digital electronics

Niharika R · @niharikaravi

intern, cyphertech solutions pvt.ltd

Fresher

Prashanth S · @sai

Fresher

digital electronics verilog system verilog system verilog assertion universal verification methodology

SHWETA JADHAV · @jadhavshweta

Hardware Design Engineer, Lewiz Communications

2+ Years

RTL Design AXI4 AXILITE Digital Circuits AXIStream Verilog TCL Scripting Basics of System verilog

Shashank Kambli · @sskambli

embedded developer, asma embedded solutions

Fresher

Embedded System Design Embedded Development Embedded Design Keil VMware Microcontroller C Xilinx HDL Embedded C Verilog

GOWRI SHANKAR KOTA · @gowri

Fresher

VHDL Verilog FPGA RTL Design Synthesis Simulation Testbench Timing Analysis Logic Synthesis.circuit design soldering digital circuits

Prudhvi Raj Botsa · @prudhvi

Software Engineer, HCL Technologies

2+ Years

Linux Networking Programming knowledge on: Python Verilog Tools: Xschem ngspice Magic VLSI Quartus Prime Operating systems like windows linux