talent skill-clock-tree-synthesis - Lucres

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Fresher

Timing closure Floorplanning Clock tree synthesis Place and Route Static timing analysis Physical verification Signal integrity analysis

Seniour design engineer - II, Alphawave Semi

3+ Years

GOWRI SHANKAR KOTA

Fresher

VHDL Verilog FPGA RTL Design Synthesis Simulation Testbench Timing Analysis Logic Synthesis.circuit design soldering digital circuits